Since the invention of non-volatile memory cells having both electrically erasable and electrically programmable capabilities as disclosed in U.S. Pat. No. 4,115,914 issued to Harari on Sept. 26, 1978; U.S. Pat. No. 4,203,158 issued to Frohman-Bentchkowsky et al on May 13, 1980, the high volume commercial production of EEPROMs that employ the thin tunnel dielectrics for electrically erasing and electrically programming has gradually become a reality. These EEPROMs consist of one selection device in series with a memory device that has a floating gate over the channel and the tunnel dielectric area on the drain, and a stacked control gate over the floating gate. The programming of the memory device is achieved by applying a suitable potential across the drain and the control gate of the memory device to cause charge carriers to tunnel through the tunnel dielectric from the floating gate to the drain. The erasing of the memory device is achieved by applying a suitable potential across the control gate and the drain of the memory device to cause charge carriers to tunnel through the tunnel dielectric from the drain to the floating gate. The tunnel dielectric area on the drain of the memory device is normally defined by the photoengraving technique. The area required to accommodate the tunnel dielectric area is normally large due to the dimensional limitation and the alignment tolerance of the photoengraving technology. In addition to the area requirement, the tunnel dielectric area by itself is also an important figure of merits. The smaller the tunnel dielectric area, the lower is the high voltage that is required for the programming and the erasing of the memory device. In addition, the larger the tunnel dielectric area, the higher is the defect density and the lower is the yield.